Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, flash drives, digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
A flash memory device is a type of memory in which the cells are typically grouped into blocks that can be erased and reprogrammed in blocks instead of one byte at a time. Changes in threshold voltage of the memory cells, through erasing or programming of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. The data in a cell of this type is determined by the presence or absence of the charge in the charge storage structure.
Detecting the presence or absence of the charge can be accomplished by a sense (e.g., read or program verify) operation. The sense operation is performed by a sense circuit coupled to the data lines (e.g., bit lines) of a memory array. A typical prior art sense circuit is illustrated in the memory device of FIG. 1.
The memory device comprises a memory array portion 101, a multiplexing circuit 115, and a sense circuit 100 with dynamic data cache circuitry. Since a typical sense operation is performed on alternate bit lines (e.g., even or odd bit lines), a multiplexing circuit 115 selects between the even and odd bit lines of the memory array 101. The multiplexing circuit 115 selects which bit line is enabled to the sense circuit 100.
A typical prior art sense operation of single level cells (SLC) comprises grounding the source line of the memory block to be sensed, precharging the memory block data lines (e.g., bit lines), and biasing the access lines (e.g., word lines) in order to turn on all of the word lines except the word line to be sensed. A sensed voltage is applied to the word line to be sensed and the select gates of alternate bit lines are turned on. If the bit line becomes discharged, the threshold voltage of the cell being read is less than the word line voltage. In this case, the cell is erased and is in a logical 1 state. If the bit line remains precharged, the threshold voltage of the cell being read is greater than the word line voltage that was applied to the word line being sensed. In this case, the memory cell is programmed and is in a logical 0 state. Multiple level memory cells (MLC) can be sensed in substantially the same way except multiple sense operations might be needed to sense the multiple levels.
In order to increase the amount of data stored in an integrated circuit, memory manufacturers can increase the memory density of the memory devices. One way of accomplishing this is to increase the number of memory cells on each memory device. A greater number of memory cells results in longer bit lines to connect to each of the series strings. This results in a larger resistance/capacitance (RC) for the longer bit lines.
RC is one of many elements that can affect memory device performance. The larger the RC of the bit lines the slower the memory operations since more time is needed to charge/discharge the bit lines during sense operations.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory array architecture that better manages increasing bit line resistance and/or capacitance.